My IMSAI (enshrined down in my basement) is immortalized as the teenage hacker's bedroom computer (he uses it to hack into his high school computer and improve his grades) in the movie "War Games."
An unknown chip maker named Intel had developed a complete digital computer on one single chip, the 8008, which quickly evolved into the somewhat more sophisticated 8080.
The problem was, nobody in industry or government wanted it or had a use for it.
But a tiny startup called MITS decided to sell a home computer KIT designed around this unwanted, orphaned chip, and announced their home computer via ads and a big series of Do-It-Yourself articles in Popular Electronics magazine.
This astonishing and wholly unexpected migration of digital computing from Giant Industry & Big Government to the humble cottage spare bedroom happened in 1975. The first home computers, in kit form, were horribly primitive compared to the Dells and Macs you can buy today, and cost about as much as a brand new refrigerator.
For most owners and users of modern computers, what goes on at the deepest level of the computer's guts -- how, exactly, the computer does the jobs we want it to do -- might as well be Magic or Alchemy or Astrology or Witchcraft.
Even those of us who can program a computer in a High-Level Language, like BASIC or FORTRAN or PYTHON or COBOL, are pretty much speaking to the computer in a pretty comprehensible dialect of English. These languages were designed to make programming Human-Friendly.
But the way a computer actually "thinks" and performs tasks is extremely Human-Hostile. At its "core," a digital computer can only manipulate enormously long strings of zeroes and ones, executing operations which are entirely based on Binary Arithmetic and Boolean Algebra.
This is what "thinking" really looks like inside a computer's CPU (Central Processing Unit) chip:
00010110010011001100010101110010011111010100010100100000101010101010 ...
Pathetically, most CPU's can't do any mathematics beyond simple addition of two binary numbers:
..00101011
+ 10010010
----------
..10111101
But there are all sorts of clever, nifty tricks to use simple addition to get the results of subtraction, multiplication, division, root extraction, and from there, any mathematical operation in the most advanced math textbook.
Then, beyond math tasks, digital computer CPUs can also manipulate big strings of 0's and 1's and interpret them as language text -- i.e., store and access and do all sort of tricks with Shakespeare's plays or "Histoire d'O" (1955 winner, Prix des Deux Magots).
Here is the Instruction Set of one of the earliest computer CPU chips, the Intel 8080. (The Z80 uses the same Instruction Set, it's just souped-up for faster speed.)
Here are two fairly simple, straightforward instructions. "Increment" just means to add one to whatever number resides in register C, and "decrement" subtracts one from the number in register C.
Machine Assembly
Language Language
Code Mnemonic Instruction
==========================================
OC INR C Increment register C
OD DCR C Decrement register C
OC and OD are the hexadecimal (base 16) notation of the instruction. It's a compressed notation for human convenience, but easily translated into binary, the only notation the CPU understands and can manipulate:
hex binary
=============
0C = 00001100
0D = 00001101
INR and DCR are Assembly Language mnemonics for each instruction. Assembly Language is one step friendlier for human programmers than Machine Language.
(In practice, it's really impossible for humans to work with or make sense of just 000101100100110011000101 ...)
My favorite instruction is
00 NOP No Operation
... an instruction that does absolutely nothing.
But it's an instruction, and when the CPU encounters it in a program, it must execute it, exactly as it must execute 0C or 0D.
But doing absolutely nothing takes time -- a very short but specific amount of time -- to execute. And sometimes a time delay is exactly what the programmer needs. So if at a particular point in a program, you want the computer to just sit there and twiddle its thumbs for 0.721 seconds, you might write something the CPU would execute as
DO THE NEXT INSTRUCTION 123 TIMES
NOP
I have suspicions that there are a few mistakes in this (filched) 8080 Instruction Set, but you'll get the idea. Just don't rely on it to program an automobile's engine, fuel or braking electronics, or to run the in-flight systems of an Airbus airliner, or an important system -- like Life Support -- on a rocket ship to Mars. Call Intel, get their documentation, use their authorized 8080 Instruction Set.
Here it is, here's everything the Intel 8080 Central Processing Unit chip knows how to do.
======================================
8080 Instruction Set
Add Instructions
80 ADD B Add register B
81 ADD C Add register C
82 ADD D Add register D
83 ADD E Add register E
84 ADD H Add register H
85 ADD L Add register L
86 ADD M Add memory
87 ADD A Add register A
88 ADC B Add register B with carry
89 ADC C Add register C with carry
8A ADC D Add register D with carry
8B ADC E Add register E with carry
8C ADC H Add register H with carry
8D ADC L Add register L with carry
8E ADC M Add memory with carry
8F ADC A Add register A with carry
C6 ADI Imm Add immediate
CE ACI Imm Add immediate with carry
19 DAD D Add register pair DE to HL
29 DAD H Add register pair HL to HL
39 DAD SP Add register SP to HL
09 DAD B Add register pair BC to HL
And Instructions
A0 ANA B And register B
A1 ANA C And register C
A2 ANA D And register D
A3 ANA E And register E
A4 ANA H And register H
A5 ANA L And register L
A6 ANA M And memory
A7 ANA A And register A
E6 ANI Imm And immediate
Call Instructions
C4 CNZ Addr Conditional Subroutine Call (Not Zero Flag)
CC CZ Addr Conditional Subroutine Call (Zero Flag)
CD CALL Addr Subroutine Call
D4 CNC Addr Conditional Subroutine Call (Not Carry Flag)
DC CC Addr Conditional Subroutine Call (Carry Flag)
E4 CPO Addr Conditional Subroutine Call (Parity Odd, Not Parity Flag)
EC CPE Addr Conditional Subroutine Call (Parity Even, Parity Flag)
F4 CP Addr Conditional Subroutine Call (Positive, Not Sign Flag)
FC CM Addr Conditional Subroutine Call (Minus, Sign Flag)
Compare Instructions
B8 CMP B Compare register B
B9 CMP C Compare register C
BA CMP D Compare register D
BB CMP E Compare register E
BC CMP H Compare register H
BD CMP L Compare register L
BE CMP M Compare memory
BF CMP A Compare register A
FE CPI Imm Compare immediate
Decrement Instructions
0B DCX B Decrement register pair BC to HL
0C INR B Increment register C
0D DCR B Decrement register C
13 INX D Increment register pair DE
14 INR D Increment register D
15 DCR D Decrement register D
1B DCX D Decrement register pair DE to HL
1C INR E Increment register E
1D DCR E Decrement register E
03 INX B Increment register pair BC
23 INX H Increment register pair HL
24 INR H Increment register H
25 DCR H Decrement register H
04 INR B Increment register B
2B DCX H Decrement register pair HL to HL
2C INR L Increment register L
2D DCR L Decrement register L
05 DCR B Decrement register B
33 INX SP Increment register SP
34 INR M Increment memory (HL)
35 DCR M Decrement memory (HL)
3B DCX SP Decrement register SP to HL
3C INR M Increment register A
3D DCR M Decrement register A
Exclusive Or Instructions
A8 XRA B Exclusive Or register B
A9 XRA C Exclusive Or register C
AA XRA D Exclusive Or register D
AB XRA E Exclusive Or register E
AC XRA H Exclusive Or register H
AD XRA L Exclusive Or register L
AE XRA M Exclusive Or memory
AF XRA A Exclusive Or register A
EE XRI Imm Exclusive Or immediate
Interrupt Instructions
F3 DI Disable Interrupt
FB EI Enable Interrupt
Jump Instructions
C2 JNZ Addr Conditional Jump (Not Zero Flag)
C3 JMP Addr Jump to Direct Address
CA JZ Addr Conditional Jump (Zero Flag)
D2 JNC Addr Conditional Jump (Not Carry Flag)
DA JC Addr Conditional Jump (Carry Flag)
E2 JPO Addr Conditional Jump (Parity Odd, Not Parity Flag)
E9 PCHL Jump Indirect HL
EA JPE Addr Conditional Jump (Parity Even, Parity Flag)
F2 JP Addr Conditional Jump (Positive, Not Sign Flag)
FA JM Addr Conditional Jump (Minus, Sign Flag)
Load Instructions
01 LXI B Load Immediate register pair BC
0A LDAX B
0E MVI B Move Immediate register C
11 LXI D Load Immediate register pair DE
16 MVI D Move Immediate register D
1A LDAX D
1E MVI E Move Immediate register E
21 LXI H Load Immediate register pair HL
26 MVI H Move Immediate register H
2A LHLD Addr
2E MVI L Move Immediate register L
31 LXI SP Load Immediate register SP
3A LDA Addr Load Direct
06 MVI B Move Immediate register B
3E MVI M Move Immediate register A
Move Instructions
F9 SPHL
Or Instructions
B0 ORA B Or register B
B1 ORA C Or register C
B2 ORA D Or register D
B3 ORA E Or register E
B4 ORA H Or register H
B5 ORA L Or register L
B6 ORA M Or memory
B7 ORA A Or register A
F6 ORI Imm Or immediate
Other Instructions
00 NOP No Operation
76 HLT Halt
D3 OUT Port Output from Port Direct
DB IN Port Input from Port Direct
E3 XTHL
EB XCHG
27 DAA Decimal Adjust
2F CMA Complement Accumulator
37 STC Set Carry Flag
3F CMC Complement Carry Flag
Reset Instructions
C7 RST 0 Reset 0
CF RST 4 Reset 4
D7 RST 1 Reset 1
DF RST 5 Reset 5
E7 RST 2 Reset 2
EF RST 6 Reset 6
F7 RST 3 Reset 3
FF RST 7 Reset 7
Return Instructions
C0 RNZ Addr Conditional Subroutine Return (Not Zero Flag)
C8 RZ Addr Conditional Subroutine Return (Zero Flag)
C9 RET Addr Subroutine Return
D0 RNC Addr Conditional Subroutine Return (Not Carry Flag)
D8 RC Addr Conditional Subroutine Return (Carry Flag)
E0 RPO Addr Conditional Subroutine Return (Parity Odd, Not Parity Flag)
E8 RPE Addr Conditional Subroutine Return (Parity Even, Parity Flag)
F0 RP Addr Conditional Subroutine Return (Positive, Not Sign Flag)
F8 RM Addr Conditional Subroutine Return (Minus, Sign Flag)
Rotate Instructions
0F RRC Rotate Right
17 RAL Rotate Left with Carry
1F RAR Rotate Right with Carry
07 RLC Rotate Left
Stack Instructions
C1 POP B Pop register pair BC
C5 PUSH B Push register pair BC
D1 POP D Pop register pair DE
D5 PUSH D Push register pair DE
E1 POP H Pop register pair HL
E5 PUSH H Push register pair HL
F1 POP SP Pop register pair PSW & A
F5 PUSH SP Push register pair PSW & A
Store Instructions
70 MOV M,B Store register B
71 MOV M,C Store register C
72 MOV M,D Store register D
73 MOV M,E Store register E
74 MOV M,H Store register H
75 MOV M,L Store register L
77 MOV M,A Store register A
12 STAX D
02 STAX B
22 SHLD Addr
36 MVI M Move Immediate memory (HL)
3A LDA Addr Load Direct
Store Instructions
70 MOV M,B Store register B
71 MOV M,C Store register C
72 MOV M,D Store register D
73 MOV M,E Store register E
74 MOV M,H Store register H
75 MOV M,L Store register L
77 MOV M,A Store register A
12 STAX D
02 STAX B
22 SHLD Addr
36 MVI M Move Immediate memory (HL)
3A LDA Addr Load Direct
Subtraction Instructions
90 SUB B Subtract register B
91 SUB C Subtract register C
92 SUB D Subtract register D
93 SUB E Subtract register E
94 SUB H Subtract register H
95 SUB L Subtract register L
96 SUB M Subtract memory
97 SUB A Subtract register A
98 SBB B Subtract register B with borrow
99 SBB C Subtract register C with borrow
9A SBB D Subtract register D with borrow
9B SBB E Subtract register E with borrow
9C SBB H Subtract register H with borrow
9D SBB L Subtract register L with borrow
9E SBB M Subtract memory with borrow
9F SBB A Subtract register A with borrow
D6 SUI Imm Subtract immediate
DE SBI Imm Subtract immediate with borrow
